A typical semiconductor device comprises a plurality of generally parallel conductive lines, typically made of a conductive material, such as polysilicon or a metal, or a stacked layer of conductive materials. These conductive lines form parts of numerous integrated circuits of semiconductor devices on a semiconductor chip. During operation of a semiconductor device, a conductive line 10 carries current I.sub.10, which can move in either direction, as depicted in FIG. 1. This corresponds to negative (positive) charges moving in a direction opposite (same) to the direction of I.sub.10. Consider two neighboring interconnect lines in FIG. 2. When line 20 is charged up, which can be represented by accumulation of positive charges, negative charges will be induced in line 21. These opposite charges attract each other, resulting in accumulation of charges on the metal surfaces facing each other, as is shown in FIG. 2. The coupling capacitance can be approximated by the formula EQU C=K*(t*L)/S
wherein K* represents the dielectric constant of the material between and surrounding the conductive lines, L is the length of the conductive line, W is the width of the conductive lines, S is the distance between the conductive lines, and t* is the thickness of the conductive lines.
The escalating requirements for high density and performance associated with ultra large scale integration require responsive changes, which is considered one of the most demanding aspects of ultra large scale integration technology. High density demands for ultra large scale integration of semiconductor wiring, which require increasingly denser arrays with minimal spacing between conductive lines. The objective is hindered by the fact that denser arrays and smaller line widths result in larger sidewalls of the metal lines and much larger coupling capacitances. In fact, for 0.5 micron technology and below, the coupling capacitance dominates the total capacitance loading of metal lines. This increase of capacitance loading, and, therefore, interconnect delay, combined with increasingly faster transistors results in a circuit where the interconnect delay dominates the total circuit delay. Thus, there exists a great need for a way to reduce interconnect capacitances. Thus, the combined requirements of high speed and high density conductive wiring patterns poses a challenge which, to date, has not been satisfactorily achieved.
The adverse impact of capacitive coupling on the operation of a semiconductor device generated by neighboring conductive lines spaced apart by a distance greater than about 1.0 micron is tolerable. However, with interwiring spacings of less than about 1.0 micron, such as less than about 0.7 microns, particularly less than about 0.5 microns, in response to the escalating requirements for density and performance associated with ultra large scale integration, the adverse consequences of the capacitive coupling effect, particularly the reduction in circuit speed, create serious problems, which require reduction of the capacitive coupling effect.
Typically, a semiconductor chip comprises a plurality of semiconductor devices each of which has one or more layers containing a plurality of conductive lines situated in a common plane which function in one or more circuits. Thus, as the interwiring spacing is reduced below 1.0 micron, particularly below 0.5 microns, the problems generated by the capacitive coupling effect become particularly acute. Moreover, semiconductor chips are conventionally placed on a printed circuit board and interconnected by a plurality of conductive wires which also generate a capacitive coupling or, more specifically, electromagnetic wave coupling effect. In addition, a plurality of semiconductor chips are conventionally interconnected in a multicomponent module by a plurality of conductive wires which generate a capacitive coupling effect.
In the manufacturing of a semiconductor device, after a conductive layer is etched to form a plurality of conductive lines, a dielectric layer is deposited to fill the interwiring spacings, and then planarized, as by etching or chemical-mechanical polishing. Silicon dioxide is conventionally employed as the dielectric material in forming dielectric layers. Currently, research in underway to resolve the capacitive coupling effect by developing materials having a lower dielectric constant than silicon dioxide to form dielectric layers in which the conductive lines are situated. However, this approach has not met with any degree of success, primarily because of the problems engendered by resorting to a material other than silicon dioxide to form a dielectric layer.
During the manufacturer of a semiconductor device, numerous process operations are performed in connection with a dielectric layer, such as deposition, etching and planarization. As a result, numerous process parameters have been developed which are linked to the particular characteristics of silicon dioxide. The introduction of a different dielectric material, other than silicon dioxide, disadvantageously carries with it new characteristics which require extensive experimentation to redefine numerous processing operations. Moreover, new materials generate different stress patterns and contamination problems.
Thus, there exists a need to solve the capacitive coupling effect generated between neighboring closely spaced conductive lines of the semiconductor device, particularly between conductive lines having interwiring spacings of less than about 1.0 micron, particularly less than about 0.5 microns, in a cost-effective expeditious manner without resorting to new materials.